1. Field of the Invention
The present invention relates to a charge pump of a phase locked loop, and more specifically, to an improved charge pump structure allowing for a smaller capacitor to be used in a loop filter of the phase locked loop.
2. Description of the Prior Art
A phase locked loop is used for frequency control. Please refer to FIG. 1. FIG. 1 is a block diagram of a phase locked loop (PLL) 10 according to the prior art. The PLL 10 contains a phase detector 12, which is used for comparing phases of two input signals IN1 and IN2. Based on a phase difference between the two input signals IN1 and IN2, the phase detector 12 then outputs either an up signal UP or a down signal DN to a charge pump circuit 14. Based on receipt of either the up signal UP or the down signal DN, the charge pump circuit 14 sends (or receives) a control current to (from) a loop filter 16. This control current is used for charging or discharging a capacitor within the loop filter 16, as will be explained more thoroughly below. Finally, a control voltage VVCONA is outputted from the loop filter 16 and fed into a voltage controlled oscillator (VCO) 18. The VCO 18 generates the output frequency IN2 based on the control voltage VVCONA that is fed into the VCO 18. Together, the phase detector 12, the charge pump circuit 14, the loop filter 16, and the VCO 18 form the PLL 10, which is a negative feedback loop.
Please refer to FIG. 2A. FIG. 2A is a diagram illustrating operation of the phase detector 12 of the PLL 10 when generating the up signal UP. As stated above, the phase detector 12 compares two inputted signals IN1 and IN2, and outputs either the up signal UP or the down signal DN based on the phase difference between IN1 and IN2. In FIG. 2A, the IN1 signal leads the IN2 signal by a phase difference of θ1. The phase detector 12 is able to detect this phase difference and then outputs a pulse of the up signal UP. A pulse width of the up signal UP is directly proportional to the phase difference θ1 between IN1 and IN2. This up signal UP is ultimately used to increase the frequency of IN2, so that IN1 and IN2 can become in-phase.
Please refer to FIG. 2B. FIG. 2B is a diagram illustrating operation of the phase detector 12 of the PLL 10 when generating the down signal DN. In FIG. 2B, the IN2 signal leads the IN1 signal by a phase difference of θ2. The phase detector 12 is able to detect this phase difference and then outputs a pulse of the down signal DN. A pulse width of the down signal DN is directly proportional to the phase difference θ2 between IN1 and IN2. This down signal DN is ultimately used to decrease the frequency of IN2, so that IN1 and IN2 can become in-phase.
Please refer to FIG. 3A. FIG. 3A is a circuit diagram of the charge pump circuit 14 and the loop filter 16 of the prior art. The charge pump circuit 14 comprises an input current source 20, which is connected to node NA of the charge pump circuit 14, that inputs a current with a magnitude of I, and an output current source 22, which is connected to node NB of the charge pump circuit 14, that outputs a current with a magnitude of I. The charge pump circuit 14 further comprises an up pulse switch swUP connected between node NA and output node VCONA, and a down pulse switch swDN connected between node VCONA and node NB. The loop filter 16 comprises a resistor R connected between the output node VCONA and an intermediate node VCON, and a capacitor C connected between the intermediate node VCON and ground.
When a pulse of the up signal UP is received from the phase detector 12, the up pulse switch swUP is programmed to close for charging the capacitor C. At all other times, the up pulse switch swUP remains open. On the other hand, when a pulse of the down signal DN is received from the phase detector 12, the down pulse switch swDN is programmed to close for discharging the capacitor C. At all other times, the down pulse switch swDN remains open. As shown in FIG. 3A, both the up pulse switch swUP and the down pulse switch swDN are shown open since neither the up signal UP nor the down signal DN are received by the charge pump circuit 14. Therefore, no current is able to flow from the charge pump circuit 14 to the loop filter 16 in order to charge or discharge the capacitor C.
Please refer to FIG. 3B. FIG. 3B is a circuit diagram of the prior art charge pump circuit 14 and loop filter 16 in a charging mode. In FIG. 3B, the charge pump circuit 14 receives a pulse of the up signal UP from the phase detector 12. Therefore, the up pulse switch swUP is closed and the down pulse switch swDN is open. A dotted line is shown illustrating a path of current with the magnitude of I from the input current source 20 through the resistor R and through the capacitor C. Since the current I is flowing through the capacitor C, the voltage across the terminals of the capacitor C will increase, and the capacitor C will be charged according to Eqn.1 shown below.
                    i        =                  C          ⁢                                    ⅆ              v                                      ⅆ              t                                                          (        1        )            
Eqn.1 shows that the longer the current I is flowing through the capacitor C, the more charged the capacitor C will become, and the larger a voltage VVCON will be. From Eqn.1, a simple proportionality relationship can be made, which is shown in Eqn.2.
                              i          K                =                  C          K                                    (        2        )            
In Eqn.2, K is a constant. The present invention makes great use of Eqn.2, and the significance of this equation will be explained fully below. As mentioned above, the voltage VVCONA is an output voltage that it outputted from the loop filter 16 to the VCO 18 for controlling the VCO 18. Eqn.3 below shows the relationship between the voltage VVCONA and the voltage VVCON.VVCONA=IR+VVCON  (3)
Eqn.3 shows that the voltage VVCONA depends on the sum of the current I flowing through resistor R and the voltage VVCON.
Please refer to FIG. 3C. FIG. 3C is a circuit diagram of the prior art charge pump circuit 14 and loop filter 16 in a discharging mode. In FIG. 3C, the charge pump circuit 14 receives a pulse of the down signal DN from the phase detector 12. Therefore, the down pulse switch swDN is closed and the up pulse switch swUP is open. A dotted line is shown illustrating a path of current with the magnitude of I from the capacitor C through the resistor R to the output current source 22. Since the current I is leaving the capacitor C, the voltage across the terminals of the capacitor C will decrease, and the capacitor C will be discharged according to Eqn.1.
Unfortunately, when fabricating the prior art charge pump circuit 14 and loop filter 16 on an integrated circuit (IC), the area of the capacitor C takes up a very large area of the IC. Not only does this increase the cost to manufacture the ICs containing the prior art PLL 10, but it also makes it difficult to design and build smaller ICs due to the large size of the capacitor C.